GPU Training in BRICS Corporate Offsite Training Venues

This instructor-led, live training in BRICS Corporate Offsite Training Venues (online or onsite) targets beginner to intermediate developers who wish to utilize OpenACC to program heterogeneous devices and exploit their parallelism.

By the end of this training, participants will be able to:

• Set up an OpenACC development environment.
• Write and run a basic OpenACC program.
• Annotate code with OpenACC directives and clauses.
• Use OpenACC API and libraries.
• Profile, debug, and optimize OpenACC programs.

This instructor-led live training in BRICS Corporate Offsite Training Venues (online or onsite) targets beginner to intermediate developers keen on learning the fundamentals of GPU programming and the key frameworks and tools for developing GPU applications.

• Upon completing this training, participants will be able to:
  Understand the differences between CPU and GPU computing, including the benefits and challenges of GPU programming.
• Choose the right framework and tool for their GPU application.
• Create a basic GPU program that performs vector addition using one or more of the frameworks and tools.
• Use the respective APIs, languages, and libraries to query device information, allocate and deallocate device memory, copy data between host and device, launch kernels, and synchronize threads.
• Use the respective memory spaces, such as global, local, constant, and private, to optimize data transfers and memory accesses.
• Use the respective execution models, such as work-items, work-groups, threads, blocks, and grids, to control the parallelism.
• Debug and test GPU programs using tools such as CodeXL, CUDA-GDB, CUDA-MEMCHECK, and NVIDIA Nsight.
• Optimize GPU programs using techniques such as coalescing, caching, prefetching, and profiling.

This instructor-led, live training in BRICS Corporate Offsite Training Venues (online or onsite) targets beginner to intermediate developers who want to utilise diverse frameworks for GPU programming and compare their features, performance, and compatibility.

Upon completing this training, participants will be able to:

• Set up a development environment featuring the OpenCL SDK, CUDA Toolkit, ROCm Platform, a device supporting OpenCL, CUDA, or ROCm, and Visual Studio Code.
• Develop a basic GPU program performing vector addition using OpenCL, CUDA, and ROCm, and compare the syntax, structure, and execution of each framework.
• Employ the respective APIs to query device information, allocate and deallocate device memory, copy data between host and device, launch kernels, and synchronize threads.
• Utilise the respective languages to write kernels that execute on the device and manipulate data.
• Use the respective built-in functions, variables, and libraries to carry out common tasks and operations.
• Leverage the respective memory spaces, such as global, local, constant, and private, to optimise data transfers and memory accesses.
• Apply the respective execution models to manage the threads, blocks, and grids that define parallelism.
• Debug and test GPU programs using tools like CodeXL, CUDA-GDB, CUDA-MEMCHECK, and NVIDIA Nsight.
• Optimise GPU programs employing techniques such as coalescing, caching, prefetching, and profiling.

This instructor-led, live training in BRICS Corporate Offsite Training Venues (online or onsite) is aimed at beginner-level to intermediate-level developers who wish to install and use ROCm on Windows to program AMD GPUs and exploit their parallelism.

By the end of this training, participants will be able to:

• Set up a development environment that includes ROCm Platform, a AMD GPU, and Visual Studio Code on Windows.
• Create a basic ROCm program that performs vector addition on the GPU and retrieves the results from the GPU memory.
• Use ROCm API to query device information, allocate and deallocate device memory, copy data between host and device, launch kernels, and synchronize threads.
• Use HIP language to write kernels that execute on the GPU and manipulate data.
• Use HIP built-in functions, variables, and libraries to perform common tasks and operations.
• Use ROCm and HIP memory spaces, such as global, shared, constant, and local, to optimize data transfers and memory accesses.
• Use ROCm and HIP execution models to control the threads, blocks, and grids that define the parallelism.
• Debug and test ROCm and HIP programs using tools such as ROCm Debugger and ROCm Profiler.
• Optimize ROCm and HIP programs using techniques such as coalescing, caching, prefetching, and profiling.

This instructor-led, live training in BRICS Corporate Offsite Training Venues (online or onsite) is aimed at beginner-level to intermediate-level developers who wish to use ROCm and HIP to program AMD GPUs and exploit their parallelism.

By the end of this training, participants will be able to:

• Set up a development environment that includes ROCm Platform, an AMD GPU, and Visual Studio Code.
• Create a basic ROCm program that performs vector addition on the GPU and retrieves the results from the GPU memory.
• Use ROCm API to query device information, allocate and deallocate device memory, copy data between host and device, launch kernels, and synchronize threads.
• Use HIP language to write kernels that execute on the GPU and manipulate data.
• Use HIP built-in functions, variables, and libraries to perform common tasks and operations.
• Use ROCm and HIP memory spaces, such as global, shared, constant, and local, to optimize data transfers and memory accesses.
• Use ROCm and HIP execution models to control the threads, blocks, and grids that define the parallelism.
• Debug and test ROCm and HIP programs using tools such as ROCm Debugger and ROCm Profiler.
• Optimize ROCm and HIP programs using techniques such as coalescing, caching, prefetching, and profiling.

This instructor-led, live training in BRICS Corporate Offsite Training Venues (online or onsite) is aimed at beginner-level to intermediate-level developers who wish to use CUDA to program NVIDIA GPUs and exploit their parallelism.

By the end of this training, participants will be able to:

• Set up a development environment that includes CUDA Toolkit, an NVIDIA GPU, and Visual Studio Code.
• Create a basic CUDA program that performs vector addition on the GPU and retrieves the results from the GPU memory.
• Use the CUDA API to query device information, allocate and deallocate device memory, copy data between host and device, launch kernels, and synchronize threads.
• Use the CUDA C/C++ language to write kernels that execute on the GPU and manipulate data.
• Use CUDA built-in functions, variables, and libraries to perform common tasks and operations.
• Use CUDA memory spaces, such as global, shared, constant, and local, to optimize data transfers and memory accesses.
• Use the CUDA execution model to control the threads, blocks, and grids that define the parallelism.
• Debug and test CUDA programs using tools such as CUDA-GDB, CUDA-MEMCHECK, and NVIDIA Nsight.
• Optimize CUDA programs using techniques such as coalescing, caching, prefetching, and profiling.

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This instructor-led, live training in BRICS Corporate Offsite Training Venues (online or onsite) is designed for beginner-level system administrators and IT professionals who wish to install, configure, manage, and troubleshoot CUDA environments.

Upon completing this training, participants will be able to:

• Comprehend the architecture, components, and capabilities of CUDA.
• Install and configure CUDA environments.
• Manage and optimize CUDA resources.
• Debug and troubleshoot common CUDA issues.

This instructor-led, live training in BRICS Corporate Offsite Training Venues (online or onsite) is designed for beginner to intermediate-level developers who want to use OpenCL to program heterogeneous devices and leverage their parallelism.

Upon completion of this training, participants will be able to:

• Set up a development environment comprising the OpenCL SDK, an OpenCL-compatible device, and Visual Studio Code.
• Develop a fundamental OpenCL program that performs vector addition on the device and retrieves results from device memory.
• Utilize the OpenCL API to query device information, and create contexts, command queues, buffers, kernels, and events.
• Write kernels using the OpenCL C language to execute on the device and manipulate data.
• Employ OpenCL built-in functions, extensions, and libraries to carry out common tasks and operations.
• Leverage OpenCL host and device memory models to optimize data transfers and memory access.
• Use the OpenCL execution model to manage work-items, work-groups, and ND-ranges.
• Debug and test OpenCL programs using tools like CodeXL, Intel VTune, and NVIDIA Nsight.
• Optimize OpenCL programs through techniques such as vectorization, loop unrolling, local memory usage, and profiling.

This instructor-led, live training in BRICS Corporate Offsite Training Venues (online or onsite) is designed for C++ developers who intend to use CUDA to expedite applications, develop high-performance GPU kernels, and exploit parallel algorithm libraries for scientific computing, data processing, and machine learning tasks.

This instructor-led, live training in BRICS Corporate Offsite Training Venues (online or onsite) is designed for C/C++ developers who wish to utilize CUDA to accelerate compute-intensive applications, including data processing, scientific simulations, machine learning workloads, and image processing pipelines.

This instructor-led, live training in BRICS Corporate Offsite Training Venues (online or onsite) targets software developers, data analysts, and technical professionals who want to use TensorFlow 2.x and Keras to build, train, and deploy deep learning models for computer vision, natural language processing, and multimodal applications.

This instructor-led, live training programme conducted in BRICS Corporate Offsite Training Venues explores GPU programming for parallel computing, the use of various platforms, hands-on work with CUDA features, and optimization strategies using CUDA. Relevant applications include deep learning, analytics, image processing, and engineering use cases.